1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more specifically to a nonvolatile memory cell structure having a vertical channel and a double gate structure.
2. Description of the Related Art
Currently, a nonvolatile memory device has characteristics to remove and store data electrically, and store data even if electric power supply is unavailable, and therefore, it has been used widely for electronic equipment such as memory cards for music or image data and mobile phones for which constant electric power supply is impossible or electric power supply is stopped intermittently.
While a flash memory device selects one cell structure for one transistor to overcome the integrity limit of EEPROM (Electrically Erasable Programmable Read Only Memory), it makes to input or output data electrically and freely, and the demand for the flash memory device has increased rapidly along with the development of mobile and multimedia industry.
A flash memory is classified as NOR and NAND type, according to its array organization of unit cells. In a NOR type flash memory, two or more cell transistors are connected to one bit line in parallel, and in a NAND type, two or more cell transistors are connected to one bit line in series.
In a NOR type flash memory, one memory cell transistor is connected between a drain connected to a bit line and a source connected to a common source line, and therefore, a NOR type flash memory has advantages of increasing electric current of a memory cell and operating at high speed. However, unlike a NAND type flash memory, it has a difficulty in high-integration due to the increasing area of a bit line contact and a source line.
To overcome this disadvantage of a NOR type flash memory, memory size reduction has been tried.
However, the way to improve the memory integration by reducing the channel width in the planar type device structure has retained some limitations related with the semiconductor process technology and the device operation.
To overcome the said problems, especially in a SONOS memory device, attempts to make a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory device structure as a double gate structure were made (Korean Patent No. 431489). However, such attempts have the limitation on high integration due to the area of a bit line contact and source line.